Thursday, September 30, 2010

NET "SYS_CLK" CLOCK_DEDICATED_ROUTE = FALSE

FPGA error while implementing

Place:1012 - A clock IOB / reset_n component pair have been found that are not placed at an optimal clock IOB / reset site pair. The clock component is placed at site . The clock IO/ reset site can be paired if they are placed/locked in the same quadrant. The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
< NET "SYS_CLK" CLOCK_DEDICATED_ROUTE = FALSE; >

CLOCK_DEDICATED_ROUTE (Clock Dedicated Route)
The CLOCK_DEDICATED_ROUTE (Clock Dedicated Route) constraint:
• Is an advanced constraint.
• Directs the tools whether or not to follow clock placement rules for a specific
architecture.

If the constraint is not used or set to TRUE, clock placement rules must be followed.
Otherwise, placement will error. If the constraint is set to FALSE, it directs the tools to
ignore the specific clock placement rule and continue with place and route. If possible,
all clock placement rule violations should be fixed in a design in order to ensure the best
clocking performance. This constraint is intended to be used only in limited situations
when it is absolutely necessary to violate a clock placement rule. For more information
about specific clock placement rules, see the Hardware User’s Guide.

Architecture:
Applies to FPGA devices. Does not apply to CPLD devices.