Xilinx module level utilization report

 In my application, following report has been generated.
For example, the "door_sens" module have "85/85" in the slices tab, but "hdlc1" have "126/467" on the same field.

What does that mean ?

* Slices can be packed with basic elements from multiple hierarchies.
  Therefore, a slice will be counted in every hierarchical module
  that each of its packed basic elements belong to.
** For each column, there are two numbers reported a / b
a  is the number of elements that belong to that specific hierarchical module.
b  is the total number of elements from that hierarchical module and any lower level
   hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.

---

Module	Partition	Slices	Slice Reg	LUTs	LUTRAM	BRAM	MULT18X18	BUFG	DCM
[-] proj_top/		897/3797	80/2859	1347/4701	0/3	0/10	0/0	2/8	0/0
door_sens		85/85	71/71	105/105	0/0	0/0	0/0	0/0	0/0
[+] hdlc1		126/467	113/464	106/652	0/0	0/2	0/0	0/0	0/0
[+] hdlc2		120/465	113/470	98/644	0/0	0/2	0/0	0/0	0/0
inp_scan		685/685	631/631	735/735	0/0	0/0	0/0	0/0	0/0
[+] uart0		118/377	112/359	103/388	0/1	0/2	0/0	0/2	0/0
[+] uart1		123/381	112/359	104/389	0/1	0/2	0/0	0/2	0/0
[+] uart2		123/384	114/361	112/397	0/1	0/2	0/0	0/2	0/0
watchdt		56/56	64/64	44/44	0/0	0/0	0/0	0/0	0/0

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NC Verilog : Representing digital simulations in an Analog way

After many hours of research and meticulous reading. Finally we could represent digital simulations in an analog way in Cadence, NC Verilog simulator.

Select the trace you want to show as Analog
Go to the "format" menu, select "trace", and then "Analog / Sample + Hold"

You may not see what you expect at first, but go over to the right hand side of the trace, and click on the little icon that looks like a box, and it will then display all values - you can adjust how it looks at the left hand side of the trace by click/dragging the red line - it will stretch it out in the y direction.
Still does not make sense try minimizing the waveform/ fit in the window in the simulator i.e. "=" and that should do the trick. 

Virtuoso: Steps for mixed signal simulation

Aim of this is to guide entry level engineers/ curious people to get started with Mixed signal simulation using Virtuoso environment
Note: 'à' stands for --> in this document.

a)      Virtuoso &

b)      Tools  à Library manager

Creating new Library can be done through

1)      File à new library

Note: You will be prompted to give the directory path at which the library will be created

2)      Dialog box: Technology file for trial library

Click on à Do not need process information and click okay

To copy some digital cells into the new created library

The best way to do that will be

1)      Go to the library whose cell needs to be copied

2)      Copy the cell or the view which you would like to copy. You can do this by simply right click and copy

3)      A dialog box will prompt you to give the library where u would like to copy the new cell/view files

4)      Press okay

5)      Copy problems à Check the message window for files and make a decision if you need to over write the files if they already exist during this process à Click on fix errors /Overwrite all and then press okay

6)      After copying all the desired verilog views

7)      This step is required only if we have copied views from another library. Double click on the schematic à Click on the copied view and press Q à Library name should coincide with the present working library name

Create new Config file

1)      Create the config file. File à New à Cellview  press okay

2)      New drop down menu Select view à Schematic à click on Use template à Select from drop down menu AMS

3)      Save

To populate a library with verilog cell views hierarchically from a verilog text file

Note: For populate you have to be in the config view.

            This step is important for viewing the signals through a hierarchical way/ internal signals.

1)      Populate à File Populate à

2)      From Section à Browse to the path of the top level verilog file

3)      To Section à From the drop down menu select the New Created Library

4)      View à Verilog e.g. instead of module

5)      Tick on the update library list

6)      Click on the Update icon in the config view

7)      Save all the changes made

To run the simulation

1)      Double click on config

2)      Dialog box will emerge à yes for configuration and top cell view

3)      Schematic editor window click Launch à ADE L

4)      Simulation window, Setup à Simulator à AMS

5)      Simulation window, Analysis à Stop Time to be specified

6)      Simulation window, To view the outputs: Go to à Select from HED for hierarchical digital signals / Select on schematic for available signals to be probed