Overloaded Operator '"+"' does not match its parameter profile

The error was really frustrating for electronic design engineer who mostly designed logic with verilog and now have to shift to vhdl

----- The above program gives the above error --------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.numeric_bit.all;

--- entity ----
--------------
architecture -----
process (*)
begin
...
addr <= addr - 1 ;
    data <= data + 1;
end process
-- error message comes as
: (line 57): Overloaded Operator '"-"' does not match its parameter profile
Error: CSVHEX0004: pci_mem_write_interface.vhd: (line 58):
Overloaded Operator '"+"' does not match its parameter profile

--- error is resolved by using a package

use ieee.numeric_std.all;