VHDL: input_output_control ncsim error

Ncsim error obsereved due to input_output_control

Error observed is this:-
ASSERT/FAILURE (time 3785380 NS) from process :input_output_control (architecture <>: <>:test)
Simulation Completed Sucessfully
Assertion at 3785380 NS + 0
/*_tb.vhd:739 assert false report "Simulation Completed Sucessfully" severity failure;
ncsim> exit

Resolution for this is to check the paths if there any files read in the test bench or behavioural model.
Please do rectify the paths and the issue will be fixed.

What is an X in digital design?

An X implies that a signal value is unknown (cannot be positively determined) and can be either one or zero. Unknown signal states are common while debugging simulation results and typically signify uninitialized signals or signals driven by more than one driver. In post layout simulations, they can also indicate a timing violation.

On the board / In reality there is nothing implies to 'X' but what it implies is that the result is not known/ cannot be predicted. The situation which we do not like to be in