vhdl use entity : vhdl top and verilog modules

         use entity pvrlib.spi_vcomp(module);
                          |
ncvhdl_p: *E,SELLIB (/user/kxa/work/spi_testing/main/spi_master_slave_test.vhd,1113|26): unit (spi_vcomp:module) not found in library (pvrlib).
        errors: 1, warnings: 0
irun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting.

Whats New in '93

In VHDL-93, an entity-architecture pair may be directly instantiated, i.e. a component need not be declared. This is more compact, but does not allow the flexibility of configuration.
DIRECT: entity HA_ENTITY(HA_ARCH) port map(A, B, S, C);
In VHDL-93, a configuration specification for a component (or instance) may legally be overridden by a configuration declaration for the same item. This was not allowed in VHDL-87.

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If you are using legacy code i.e. vhdl 87 and the top level files are trying to call some verilog modules. In

VHDL 87 used to use configuration but vhdl 93 do not require configuration to be used. Accept use the switch -v93 when using irun from cadence
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for all: sip_mm
use entity work.sip_mm(module);
end for
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