Xilinx module level utilization report

 In my application, following report has been generated.
For example, the "door_sens" module have "85/85" in the slices tab, but "hdlc1" have "126/467" on the same field.

What does that mean ?

* Slices can be packed with basic elements from multiple hierarchies.
  Therefore, a slice will be counted in every hierarchical module
  that each of its packed basic elements belong to.
** For each column, there are two numbers reported a / b
a  is the number of elements that belong to that specific hierarchical module.
b  is the total number of elements from that hierarchical module and any lower level
   hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.

---

Module	Partition	Slices	Slice Reg	LUTs	LUTRAM	BRAM	MULT18X18	BUFG	DCM
[-] proj_top/		897/3797	80/2859	1347/4701	0/3	0/10	0/0	2/8	0/0
door_sens		85/85	71/71	105/105	0/0	0/0	0/0	0/0	0/0
[+] hdlc1		126/467	113/464	106/652	0/0	0/2	0/0	0/0	0/0
[+] hdlc2		120/465	113/470	98/644	0/0	0/2	0/0	0/0	0/0
inp_scan		685/685	631/631	735/735	0/0	0/0	0/0	0/0	0/0
[+] uart0		118/377	112/359	103/388	0/1	0/2	0/0	0/2	0/0
[+] uart1		123/381	112/359	104/389	0/1	0/2	0/0	0/2	0/0
[+] uart2		123/384	114/361	112/397	0/1	0/2	0/0	0/2	0/0
watchdt		56/56	64/64	44/44	0/0	0/0	0/0	0/0	0/0

Failing conventionally

"Failing conventionally is acceptable" Warren Buffett once said, "is the way to go
There are many people making a very good living out failing alongside everybody else

"Where you are is not who you are"
"Ants don't quit"
Uncertainty is the only certainty in life

Business Philosophy:-
Our philosophy is simple - we never miss a deadline, we never exceed the budget, and the work we produce is impeccably realised.

NC Verilog : Representing digital simulations in an Analog way

After many hours of research and meticulous reading. Finally we could represent digital simulations in an analog way in Cadence, NC Verilog simulator.

Select the trace you want to show as Analog
Go to the "format" menu, select "trace", and then "Analog / Sample + Hold"

You may not see what you expect at first, but go over to the right hand side of the trace, and click on the little icon that looks like a box, and it will then display all values - you can adjust how it looks at the left hand side of the trace by click/dragging the red line - it will stretch it out in the y direction.
Still does not make sense try minimizing the waveform/ fit in the window in the simulator i.e. "=" and that should do the trick. 

Virtuoso: Steps for mixed signal simulation

Aim of this is to guide entry level engineers/ curious people to get started with Mixed signal simulation using Virtuoso environment
Note: 'à' stands for --> in this document.

a)      Virtuoso &

b)      Tools  à Library manager

Creating new Library can be done through

1)      File à new library

Note: You will be prompted to give the directory path at which the library will be created

2)      Dialog box: Technology file for trial library

Click on à Do not need process information and click okay

To copy some digital cells into the new created library

The best way to do that will be

1)      Go to the library whose cell needs to be copied

2)      Copy the cell or the view which you would like to copy. You can do this by simply right click and copy

3)      A dialog box will prompt you to give the library where u would like to copy the new cell/view files

4)      Press okay

5)      Copy problems à Check the message window for files and make a decision if you need to over write the files if they already exist during this process à Click on fix errors /Overwrite all and then press okay

6)      After copying all the desired verilog views

7)      This step is required only if we have copied views from another library. Double click on the schematic à Click on the copied view and press Q à Library name should coincide with the present working library name

Create new Config file

1)      Create the config file. File à New à Cellview  press okay

2)      New drop down menu Select view à Schematic à click on Use template à Select from drop down menu AMS

3)      Save

To populate a library with verilog cell views hierarchically from a verilog text file

Note: For populate you have to be in the config view.

            This step is important for viewing the signals through a hierarchical way/ internal signals.

1)      Populate à File Populate à

2)      From Section à Browse to the path of the top level verilog file

3)      To Section à From the drop down menu select the New Created Library

4)      View à Verilog e.g. instead of module

5)      Tick on the update library list

6)      Click on the Update icon in the config view

7)      Save all the changes made

To run the simulation

1)      Double click on config

2)      Dialog box will emerge à yes for configuration and top cell view

3)      Schematic editor window click Launch à ADE L

4)      Simulation window, Setup à Simulator à AMS

5)      Simulation window, Analysis à Stop Time to be specified

6)      Simulation window, To view the outputs: Go to à Select from HED for hierarchical digital signals / Select on schematic for available signals to be probed

NET "SYS_CLK" CLOCK_DEDICATED_ROUTE = FALSE

FPGA error while implementing

Place:1012 - A clock IOB / reset_n component pair have been found that are not placed at an optimal clock IOB / reset site pair. The clock component is placed at site . The clock IO/ reset site can be paired if they are placed/locked in the same quadrant. The IO component is placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule.
< NET "SYS_CLK" CLOCK_DEDICATED_ROUTE = FALSE; >

CLOCK_DEDICATED_ROUTE (Clock Dedicated Route)
The CLOCK_DEDICATED_ROUTE (Clock Dedicated Route) constraint:
• Is an advanced constraint.
• Directs the tools whether or not to follow clock placement rules for a specific
architecture.

If the constraint is not used or set to TRUE, clock placement rules must be followed.
Otherwise, placement will error. If the constraint is set to FALSE, it directs the tools to
ignore the specific clock placement rule and continue with place and route. If possible,
all clock placement rule violations should be fixed in a design in order to ensure the best
clocking performance. This constraint is intended to be used only in limited situations
when it is absolutely necessary to violate a clock placement rule. For more information
about specific clock placement rules, see the Hardware User’s Guide.

Architecture:
Applies to FPGA devices. Does not apply to CPLD devices.

Palak for Bachelors

I thought of making Palak today.
I do not like the color of Palak and also had a bitter taste sometimes.

Curious about can I do some thing good and eat healthy. So tried making Palak after taking tips from wife Nija.
This blog is a testimonial for making good palak which tastes good and is also healthy.

The purpose of writing this is for people who are bachelors/ married like me and Nija but still staying apart but would like enjoy a healthy meal sometimes :)
Secondly who want to prepare healthy food but fast.
Thirdly get confused with a long list of things required for preparing palak. 

Ingredients required for making great Palak gravy (This is for 2 people only)
Essential
* Palak i.e. 3-4 bunches
* Onion i.e. One and half onion finely cut
* garlic i.e. 3 peaces finely cut
* Tomato i.e. 2 is ideal
* Chilli powder i.e. half spoon will be fine
* Salt i.e. as per taste

Nice to have ingredients are
* Indian spices
* Jeera
* Paneer (if you want to make Palak Paneer or a fan of Paneer)

Note: To prepare Palak in 20 minutes you need two gas burners
a) Burner 1 On one burner after washing the palak boil it for 2-3 minutes
Note: Stem of the palak should be avoided.
b) Burner 2 Add 2 teaspoon of oil, make use of Indian spices and Jeera right now and let it fry for some time. Or directly move to Ginger.
c) In the mean time cut the onions and add to the Ginger paste with some salt.
d) Let the onions become brown.
Note: Its best to keep the gas burner slow at this stage.
e) Remove the palak which is cooked and then use the mixer to make a thin paste
f) Till the onions become brown please cut the tomatoes. Tomatoes should be finely chopped if possible.
g) Add the tomatoes to the brown onions with some more salt.
h) Add some red chili powder (This depends on how spicy you want to have the curry)
h) Add the grinded Palak to the onions and the tomatoe paste.

Optional if you have /like paneer
i) Add paneer/ cheese to Palak with some cream and make Palak Paneer.

Its quite simple and ready to eat in 20 minutes
One of the book says the best way to reduce weight is to eat food fresh :)
Note: Food cooked 3 hrs before is still considered fresh as per the book

Problems of employment and how to tackle them

This blog only covers what to do when you do get cheated by the employer and what are the UK government employment policies and process.

This blog does not cover information on
a) Hours of work
b) What should be the pay
c) How to avoid exploitation

My personal experience is that asian employers exploit you the most. I am sure there will be exceptions on this and it is not the rule of thumb.

I have always come across situations where people try to exploit and misuse the process which is actually meant to improve the quality of our life.
The most common of all are
a) Do not pay for the number's of hours worked
This is very common in the service industry. I have always seen student's who come to the UK are exploited a lot or they want to be exploited. They give them more hours to work but do not pay the minimum wages. This is a win win situation for the employer and the employee.
Note: This is against the law :)
But there are instances that you work and still do not get paid. In such instances we should fight for what is unfair. According to me employer and the employee both are breaking the law. Employee is breaking the law by not reporting this atrocities and employer is misusing his position.
b) Misuse of the timesheets
This is also one of the common things employees misuse. Its always good to keep a record of time we have worked if you are paid on hourly basis. Though punching cards/ electronics machine has helped in solving this issue.
c) Racial abuse and mistreatment
This is one of the most disgusting thing I feel in life. Mostly this happens when people take the other person for granted. Report it to the concerned authority.

Legal process
In UK any Employment issue should be brought to the notice of employment tribunal within a period of 3 months after the incident has happened.
Claims regarding number of hours worked, racial abuse, employment issues should be reported soon as possible/ three months before the incident has occurred.

There are a lot of Solicitors who work on this issue. Most of the problems are resolved once you sent a legal notice to the employer. Its very important that a legal notice is served to the person/ company.
Attorney charges are around say 200/ 250 quid. There are some attorney's who do it for free for you as they recover the charges from the other client.

Some of the attorney who work on employment issue is 
http://www.tribunal-online.com/

http://www.employmentlaw.co.uk/

Note: Once the legal notice is served Employer will try to negotiate and try to take time so that they cross the 3 months period. This is a common mistake done. Legally employer has an advantage if you fail to inform the employment tribunal before the 3 month period.

Whizzman Ltd is a company in UK which according to my experience exploits people of asian origin. They operate a restaurant at Walthamstow, London by the name "Indian Bristo".
PWC Solicitors, Illford represent Whizzman Ltd in their wrong doing and negotiations.