Read a Text file in VHDL

-- VHDL Packages required  for textio to be inputed
use ieee.std_logic_textio.all;
use std.textio.all; -- Reading and writing from/ to a file
 
--Taking input from any  Text file
  read_file:
    process    -- read file_io.in (one time at start of simulation)
      file my_input : TEXT open READ_MODE is "C:\Flur_board\hdl\out1.txt";
      variable my_line : LINE;
      variable data_from_file : integer range 0 to 1000;
      --variable code_v : integer range 0 to 63;
     
      --variable data_from_file : LINE;
      --variable my_line : std_logic_vector(RAW_DATA-1 downto 0);
      variable my_input_line : LINE;
    begin
      write(my_line, string'("reading file"));
      writeline(output, my_line);
      loop
        wait until rising_edge(clk);
        exit when endfile(my_input);
    if (simulation_start = '1') then 
        readline(my_input, my_input_line);
    read(my_input_line,data_from_file);

    file_output <= conv_std_logic_vector(data_from_file,1001) ;
        -- process input, possibly set up signals or arrays
        writeline(output, my_input_line);  -- optional, write to std out
    end if;
      end loop;
      wait; -- one shot at time zero,
    end process read_file;
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