VHDL: input_output_control ncsim error

Ncsim error obsereved due to input_output_control

Error observed is this:-
ASSERT/FAILURE (time 3785380 NS) from process :input_output_control (architecture <>: <>:test)
Simulation Completed Sucessfully
Assertion at 3785380 NS + 0
/*_tb.vhd:739 assert false report "Simulation Completed Sucessfully" severity failure;
ncsim> exit

Resolution for this is to check the paths if there any files read in the test bench or behavioural model.
Please do rectify the paths and the issue will be fixed.